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a
FEATURES Calibrated RMS Response Excellent Temperature Stability Up to 30 dB Input Range at 2.5 GHz 700 mV rms, 10 dBm re 50 Maximum Input 0.25 dB Linear Response Up to 2.5 GHz Single Supply Operation: 2.7 V to 5.5 V Low Power: 3.3 mW at 3 V Supply Rapid Power-Down to Less than 1 A APPLICATIONS Measurement of CDMA, W-CDMA, QAM, Other Complex Modulation Waveforms RF Transmitter or Receiver Power Measurement
RFIN
2
LF to 2.5 GHz TruPwrTM Detector AD8361
FUNCTIONAL BLOCK DIAGRAMS micro_SOIC
VPOS
i
INTERNAL FILTER FLTR
TRANSCONDUCTANCE CELLS
2
AD8361 i
ERROR AMP 7.5 BUFFER ADD OFFSET SREF COMM IREF
VRMS
PWDN
BAND-GAP REFERENCE
PRODUCT DESCRIPTION
The AD8361 is a mean-responding power detector for use in highfrequency receiver and transmitter signal chains, up to 2.5 GHz. It is very easy to apply. It requires only a single supply between 2.7 V and 5.5 V, power supply decoupling capacitor and an input coupling capacitor in most applications. The output is a linear-responding dc voltage with a conversion gain of 7.5 V/V rms. An external filter capacitor can be added to increase the averaging time constant.
3.0 2.8 2.6 2.4 2.2 2.0
V rms - Volts
SOT-23-6L
VPOS RFIN
2
i
INTERNAL FILTER FLTR
TRANSCONDUCTANCE CELLS
2
AD8361 i
ERROR AMP 7.5 BUFFER
VRMS
PWDN
SUPPLY REFERENCE MODE
BAND-GAP REFERENCE COMM
INTERNAL REFERENCE MODE
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 0.1 0.2 0.3 RFIN - V rms 0.4 0.5 GROUND REFERENCE MODE
The AD8361 is intended for true power measurement of simple and complex waveforms. The device is particularly useful for measuring high crest-factor (high peak-to-rms ratio) signals, such as CDMA and W-CDMA. The AD8361 has three operating modes to accommodate a variety of analog-to-digital converter requirements: 1. Ground referenced mode, in which the origin is zero; 2. Internal reference mode, which offsets the output 350 mV above ground; 3. Supply reference mode, which offsets the output to VS/7.5. The AD8361 is specified for operation from -40C to +85C and is available in 8-lead micro_SOIC and 6-lead SOT packages. It is fabricated on a proprietary high fT silicon bipolar process.
Figure 1. Output in the Three Reference Modes, Supply 3 V, Frequency 1.9 GHz (SOT-23-6L Package Ground Reference Mode Only)
TruPwr is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD8361-SPECIFICATIONS (T = 25 C, V = 3 V, f noted.)
A S
RF
= 900 MHz, ground reference output mode, unless otherwise
Min Typ Max 2.5 Unit GHz mV rms dBm mV rms dBm pF V/V rms V/V rms dB dB dB dB dB dB dB dB dB dB V mV mV mV mV mV V V V s s A V mA A A
Parameter SIGNAL INPUT INTERFACE Frequency Range1 Linear Response Upper Limit
Condition (Input RFIN) VS = 3 V Equivalent dBm re 50 VS = 5 V Equivalent dBm re 50 (Input RFIN to Output V rms)
Input Impedance2 RMS CONVERSION Conversion Gain Dynamic Range 0.25 dB Error4 1 dB Error 2 dB Error Intercept-Induced Dynamic Range Reduction 5, 6 Deviation from CW Response
390 4.9 660 9.4 225 1 7.5
fRF = 100 MHz, VS = 5 V Error Referred to Best Fit Line 3 CW Input, -40C < TA < +85C CW Input, -40C < TA < +85C CW Input, -40C < TA < +85C CW Input, VS = 5 V, -40C < TA < +85C Internal Reference Mode Supply Reference Mode, VS = 3.0 V Supply Reference Mode, VS = 5.0 V 5.5 dB Peak-to-Average Ratio (IS95 Reverse Link) 12 dB Peak-to-Average Ratio (W-CDMA 4 Channels) 18 dB Peak-to-Average Ratio (W-CDMA 15 Channels) Inferred from Best Fit Line 3 0 V at SREF, VS at IREF fRF = 100 MHz, VS = 5 V 0 V at SREF, IREF Open fRF = 100 MHz, VS = 5 V 0 V at IREF, 3 V at SREF fRF = 100 MHz, VS = 5 V 0 V at IREF, VS at SREF 2.7 VS 5.5 V, -40C < TA < +85C 2.7 VS 5.5 V, -40C < TA < +85C 2 pF at FLTR Pin, 224 mV rms at RFIN 100 nF at FLTR Pin, 224 mV rms at RFIN
6.5 14 23 26 30 1 1 1.5 0.2 1.0 1.2 0 -50 350 300 400 590 VS/7.5 VS - 0.5
8.5
OUTPUT INTERCEPT5 Ground Reference Mode (GRM) Internal Reference Mode (IRM) Supply Reference Mode (SRM)
+150 500 750
POWER-DOWN INTERFACE PWDN HI Threshold PWDN LO Threshold Power-Up Response Time PWDN Bias Current POWER SUPPLIES Operating Range Quiescent Current Power-Down Current
0.1 5 320 <1 2.7 1.1 <1 10 x VS 5.5
-40C < TA < +85C 0 mV rms at RFIN, PWDN Input LO 7 GRM or IRM, 0 mV rms at RFIN, PWDN Input HI SRM, 0 mV rms at RFIN, PWDN Input HI
NOTES 1 Operation at arbitrarily low frequencies is possible; see Applications section. 2 Figure 13 and Figure 40 show impedance vs. frequency for the micro_SOIC and SOT respectively. 3 Calculated using linear regression. 4 Compensated for output reference temperature drift; see Applications section. 5 SOT-23-6L operates in ground reference mode only. 6 The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figures 35 and 36. 7 Supply current is input level dependant; see Figure 12. Specifications subject to change without notice.
-2-
REV. A
AD8361
ABSOLUTE MAXIMUM RATINGS 1 PIN FUNCTION DESCRIPTIONS
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V SREF, PWDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VS IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS - 0.3 V, VS RFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V rms Equivalent Power re 50 . . . . . . . . . . . . . . . . . . . 13 dBm Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 200 mW SOT-23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mW micro_SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for the device in free air. SOT-23-6L: JA = 230C/W; JC = 92C/W. micro_SOIC: JA = 200C/W; JC = 44C/W.
Pin Micro SOT Name 1 2 6 VPOS
Description
3
5
4
4
PIN CONFIGURATIONS micro_SOIC
VPOS 1 IREF 2 RFIN 3 PWDN 4
5 6
AD8361
8 SREF 7 VRMS 6 FLTR 5 COMM
2 3
7
1
SOT-23-6L
VRMS 1 6 VPOS 5 RFIN 4 PWDN
8
AD8361
COMM 2 FLTR 3
Supply Voltage Pin. Operational range 2.7 V to 5.5 V. IREF Output Reference Control Pin. Internal reference mode enabled when pin is left open. Otherwise, this pin should be tied to VPOS. DO NOT ground this pin. RFIN Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance is 225 . PWDN Power-Down Pin. For the device to operate as a detector it needs a logical low input (less than 100 mV). When a logic high (greater than VS - 0.5 V) is applied, the device is turned off and the supply current goes to nearly zero (ground and internal reference mode less than 1 A, supply reference mode VS divided by 100 k). COMM Device Ground Pin. FLTR By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is lowered. The onchip filter is formed with 27 pF 2 k for small input signals. VRMS Output Pin. Near-rail-to-rail voltage output with limited current drive capabilities. Expected load >10 k to ground. SREF Supply Reference Control Pin. To enable supply reference mode this pin must be connected to VPOS, otherwise it should be connected to COMM (ground).
ORDERING GUIDE
Model AD8361ARM* AD8361ARM-REEL AD8361ARM-REEL7 AD8361ART-REEL AD8361ART-REEL7 AD8361-EVAL AD8361ART-EVAL
*Device branded as J3A.
Temperature Range -40C to +85C
Package Description Tube, 8-Lead micro_SOIC 13" Tape and Reel 7" Tape and Reel 13" Tape and Reel 7" Tape and Reel Evaluation Board micro_SOIC Evaluation Board SOT-23-6L
Package Option RM-8
RT-6
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8361 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD8361-Typical Performance Characteristics
2.8 2.6 2.4 2.2 2.0
OUTPUT - Volts
3.0
900MHz
2.5 2.0
100MHz
1900MHz
1.5 1.0
ERROR - dB
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 0.1 0.2 0.3 INPUT - V rms 0.4 0.5 2.5GHz
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.01 0.02 (-21dBm) 0.1 (-7dBm) INPUT - V rms 0.4 (+5dBm) MEAN 3 SIGMA
Figure 2. Output vs. Input Level, Frequencies 100 MHz, 900 MHz, 1900 MHz, and 2500 MHz, Supply 2.7 V, Ground Reference Mode, micro_SOIC
Figure 5. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, Sine Wave, Supply 3.0 V, Frequency 900 MHz
5.5 5.0 4.5 4.0
OUTPUT - Volts
5.5V
3.0 2.5 2.0
5.0V 3.0V
1.5 1.0
ERROR - dB
2.7V
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 0.1 0.2 0.3 0.4 0.5 INPUT - V rms 0.6 0.7 0.8
0.5 0 -0.5 -1.0 MEAN -1.5 -2.0 -2.5 -3.0 0.01 0.02 (-21dBm) 0.1 (-7dBm) INPUT - V rms 0.6 (+8.6dBm) 3 SIGMA
Figure 3. Output vs. Input Level, Supply 2.7 V, 3.0 V, 5.0 V, and 5.5 V, Frequency 900 MHz
Figure 6. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, Sine-Wave, Supply 5.0 V, Frequency 900 MHz
3.0 2.5 2.0 1.5 IS95 REVERSE LINK
5.0 4.5 4.0 3.5
OUTPUT - Volts
IS95 REVERSE LINK
CW
1.0
ERROR - dB
CW
3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 0.1 0.2 0.3 0.4 0.5 INPUT - V rms 0.6 0.7 0.8 WCDMA 4- AND 15-CHANNEL
0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.01 0.02 0.1 INPUT - V rms 0.2 0.6 1.0 15-CHANNEL 4-CHANNEL
Figure 4. Output vs. Input Level with Different Waveforms Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel and W-CDMA 15-Channel, Supply 5.0 V
Figure 7. Error from CW Linear Reference vs. Input with Different Waveforms Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel and W-CDMA 15-Channel, Supply 3.0 V, Frequency 900 MHz
-4-
REV. A
AD8361
3.0 2.5 2.0 1.5 1.0 3.0 2.5 2.0 1.5 1.0
ERROR - dB
+85 C
ERROR - dB
0.5 0 -0.5 -1.0 MEAN -1.5 -2.0 -2.5 -3.0 0.01 0.02 (-21dBm) 0.1 (-7dBm) INPUT - V rms 0.4 (+5dBm) 3 SIGMA
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.01 0.02 (-21dBm) 0.1 (-7dBm) INPUT - V rms 0.4 (+5dBm) -40 C
Figure 8. Error from CW Linear Reference vs. Input, 3 Sigma to Either Side of Mean, IS95 Reverse Link Signal, Supply 3.0 V, Frequency 900 MHz
3.0 2.5 2.0
Figure 11. Output Delta from +25C vs. Input Level, 3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V, Frequency 1900 MHz, Temperature -40C to +85C
11 10 9 VS = 5V INPUT OUT OF RANGE -40 C VS = 3V INPUT OUT OF RANGE +85 C 5 +25 C 4 3 2 1 0 -40 C 0 0.1 0.2 0.3 0.4 0.5 INPUT - V rms 0.6 0.7 0.8 +85 C +25 C
SUPPLY CURRENT - mA
1.5 1.0
8 7 6
ERROR - dB
0.5 0 -0.5 -1.0 MEAN -1.5 -2.0 -2.5 -3.0 0.01 0.02 (-21dBm) 0.1 (-7dBm) INPUT - V rms 0.6 (+8.6dBm) 3 SIGMA
Figure 9. Error from CW Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, IS95 Reverse Link Signal, Supply 5.0 V, Frequency 900 MHz
3.0 2.5 2.0
Figure 12. Supply Current vs. Input Level, Supplies 3.0 V, and 5.0 V, Temperatures -40C, +25C, and +85C
250
1.8 +25 C +85 C 1.6
1.5 1.0
SHUNT RESISTANCE -
+85 C
-40 C +85 C 150
1.4 1.2 1.0
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.01 0.02 (-21dBm) 0.1 (-7dBm) INPUT - V rms 0.4 (+5dBm) -40 C
100 +25 C 0.8 -40 C 50 0.6
0 0 500 1500 1000 FREQUENCY - MHz 2000
0.4 2500
Figure 10. Output Delta from +25C vs. Input Level, 3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V, Frequency 900 MHz, Temperature -40C to +85C
Figure 13. Input Impedance vs. Frequency, Supply 3 V, Temperatures -40C, +25C, and +85C, micro_SOIC (See Applications for SOT-23-6L Data)
REV. A
-5-
SHUNT CAPACITANCE - pF
200
ERROR - dB
AD8361
0.03 0.02 INTERCEPT CHANGE - Volts 0.01 0.00 -0.01 -0.02 MEAN -0.03 -0.04
-0.04 0.18 0.16 0.14
GAIN CHANGE - V/V rms
0.12 0.10 MEAN 0.08 0.06 0.04 0.02 0.00 -0.02 3 SIGMA
3 SIGMA
-0.05
-0.06
-40
-20
0 20 40 TEMPERATURE - C
60
80
100
-40
-20
0 20 40 TEMPERATURE - C
60
80
100
Figure 14. Output Reference Change vs. Temperature, Supply 3 V, Ground Reference Mode
Figure 17. Conversion Gain Change vs. Temperature, Supply 3 V, Ground Reference Mode, Frequency 900 MHz
0.02
0.18 0.16
INTERCEPT CHANGE - Volts
0.01
GAIN CHANGE - V/V rms
0.14 0.12 0.10 MEAN 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 3 SIGMA
0.00
-0.01 MEAN -0.02 3 SIGMA
-0.03
-40
-20
0 20 40 TEMPERATURE - C
60
80
100
-0.06 -40 -20 0 20 40 TEMPERATURE - C 60 80 100
Figure 15. Output Reference Change vs. Temperature, Supply 3 V, Internal Reference Mode (micro_SOIC Only)
Figure 18. Conversion Gain Change vs. Temperature, Supply 3 V, Internal Reference Mode, Frequency 900 MHz (micro_SOIC Only)
0.03 0.02 INTERCEPT CHANGE - Volts 0.01
GAIN CHANGE - V/V rms
0.18 0.16 0.14 0.12 0.10 MEAN 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 3 SIGMA
0.00 -0.01 -0.02 MEAN -0.03 -0.04 -0.05 3 SIGMA
-40
-20
0 20 40 TEMPERATURE - C
60
80
100
-0.06 -40 -20 0 20 40 TEMPERATURE - C 60 80 100
Figure 16. Output Reference Change vs. Temperature, Supply 3 V, Supply Reference Mode (micro_SOIC Only)
Figure 19. Conversion Gain Change vs. Temperature, Supply 3 V, Supply Reference Mode, Frequency 900 MHz (micro_SOIC Only)
-6-
REV. A
AD8361
GATE PULSE FOR 900MHz RF TONE 370mV 500mV PER VERTICAL DIVISION 500mV PER VERTICAL DIVISION PWDN INPUT 370mV
270mV RF INPUT
270mV
RF INPUT 67mV
67mV
25mV 5 s PER HORIZONTAL DIVISION
25mV 2 s PER HORIZONTAL DIVISION
Figure 20. Output Response to Modulated Pulse Input for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, No Filter Capacitor
Figure 23. Output Response Using Power-Down Mode for Various RF Input Levels, Supply 3 V, Frequency 900 MHz, No Filter Capacitor
GATE PULSE FOR 900MHz RF TONE 370mV 500mV PER VERTICAL DIVISION
PWDN INPUT 370mV
270mV RF INPUT 500mV PER VERTICAL DIVISION
270mV
RF INPUT 67mV
67mV
25mV 50 s PER HORIZONTAL DIVISION
25mV 20 s PER HORIZONTAL DIVISION
Figure 21. Output Response to Modulated Pulse Input for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 F Filter Capacitor
Figure 24. Output Response Using Power-Down Mode for Various RF Input Levels, Supply 3 V, Frequency 900 MHz, 0.01 F Filter Capacitor
HPE3631A POWER SUPPLY
TEK TDS784C SCOPE
HPE3631A POWER SUPPLY
TEK TDS784C SCOPE
C4 0.01 F
C2 100pF
AD8361
VPOS IREF C1 RFIN FLTR COMM SREF VRMS C3 TEK P6204 FET PROBE C5 100pF
C4 0.01 F
C2 100pF
AD8361
VPOS IREF C1 RFIN FLTR COMM SREF VRMS C3 TEK P6204 FET PROBE C5 100pF
R1 75
0.1 F PWDN
R1 75
0.1 F PWDN
HP8648B SIGNAL GENERATOR
HP8648B SIGNAL GENERATOR
HP8110A PULSE GENERATOR
Figure 22. Hardware Configuration for Output Response to Modulated Pulse Input
Figure 25. Hardware Configuration for Output Response Using Power-Down Mode
REV. A
-7-
AD8361
7.8 7.6
16 14
VS = 3V
CONVERSION GAIN - V/V rms
7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0
12 10 8 6 4 2
5.8 5.6 100 1000 CARRIER FREQUENCY - MHz
PERCENT
0 6.9
7.0
7.2 7.6 7.4 CONVERSION GAIN - V/V rms
7.8
Figure 26. Conversion Gain Change vs. Frequency, Supply 3 V, Ground Reference Mode, Frequency 100 MHz to 2500 MHz, Representative Device
Figure 29. Conversion Gain Distribution Frequency 100 MHz, Supply 5 V, Sample Size 3000
12
SUPPLY
RF INPUT 370mV 500mV PER VERTICAL DIVISION
PERCENT
12
10
270mV
8
6
67mV 25mV 20 s PER HORIZONTAL DIVISION
4
2
0 0.32 0.34 0.38 0.42 0.36 0.40 IREF MODE INTERCEPT - Volts 0.44
Figure 27. Output Response to Gating On Power Supply, for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 F Filter Capacitor
Figure 30. Output Reference, Internal Reference Mode, Supply 5 V, Sample Size 3000 (micro_SOIC Only)
AD811 50 732
HP8110A PULSE GENERATOR
12 12
10
TEK TDS784C SCOPE C2 100pF
8
C4 0.01 F
AD8361
VPOS IREF SREF VRMS C3 RFIN FLTR COMM TEK P6204 FET PROBE C5 100pF
PERCENT
6
C1 R1 75 0.1 F PWDN
4
2
HP8648B SIGNAL GENERATOR
0 0.64 0.66 0.68 0.72 0.70 SREF MODE INTERCEPT - Volts 0.74 0.76
Figure 28. Hardware Configuration for Output Response to Power Supply Gating Measurements
Figure 31. Output Reference, Supply Reference Mode, Supply 5 V, Sample Size 3000 (micro_SOIC Only)
-8-
REV. A
AD8361
CIRCUIT DESCRIPTION
The AD8361 is an rms-responding (mean power) detector providing an approach to the exact measurement of RF power that is basically independent of waveform. It achieves this function through the use of a proprietary technique in which the outputs of two identical squaring cells are balanced by the action of a high-gain error amplifier. The signal to be measured is applied to the input of the first squaring cell, which presents a nominal (LF) resistance of 225 between the pin RFIN and COMM (connected to the ground plane). Since the input pin is at a bias voltage of about 0.8 V above ground, a coupling capacitor is required. By making this an external component, the measurement range may be extended to arbitrarily low frequencies. The AD8361 responds to the voltage, VIN, at its input, by squaring this voltage to generate a current proportional to VIN squared. This is applied to an internal load resistor, across which is connected a capacitor. These form a low-pass filter, which extracts the mean of VIN squared. Although essentially voltage-responding, the associated input impedance calibrates this port in terms of equivalent power. Thus 1 mW corresponds to a voltage input of 447 mV rms. In the Application section it is shown how to match this input to 50 . The voltage across the low-pass filter, whose frequency may be arbitrarily low, is applied to one input of an error-sensing amplifier. A second identical voltage-squaring cell is used to close a negative feedback loop around this error amplifier. This second cell is driven by a fraction of the quasi-dc output voltage of the AD8361. When the voltage at the input of the second squaring cell is equal to the rms value of VIN, the loop is in a stable state, and the output then represents the rms value of the input. The feedback ratio is nominally 0.133, making the rms-dc conversion gain x7.5, that is VOUT = 7.5 x VIN rms By completing the feedback path through a second squaring cell, identical to the one receiving the signal to be measured, several benefits arise. First, scaling effects in these cells cancel; thus, the overall calibration may be accurate, even though the open-loop response of the squaring cells taken separately need not be. Note that in implementing rms-dc conversion, no reference voltage enters into the closed-loop scaling. Second, the tracking in the responses of the dual cells remains very close over temperature, leading to excellent stability of calibration. The squaring cells have very wide bandwidth with an intrinsic response from dc to microwave. However, the dynamic range of such a system is fairly small, due in part to the much larger dynamic range at the output of the squaring cells. There are practical limitations to the accuracy with which very small error signals can be sensed at the bottom end of the dynamic range, arising from small random offsets; these set the limit to the attainable accuracy at small inputs. On the other hand, the squaring cells in the AD8361 have a "Class-AB" aspect; the peak input is not limited by their quiescent bias condition, but is determined mainly by the
eventual loss of square-law conformance. Consequently, the top end of their response range occurs at a fairly large input level (about 700 mV rms) while preserving a reasonably accurate square-law response. The maximum usable range is, in practice, limited by the output swing. The rail-to-rail output stage can swing from a few millivolts above ground to less than 100 mV below the supply. An example of the output induced limit: given a gain of 7.5 and assuming a maximum output of 2.9 V with a 3 V supply; the maximum input is (2.9 V rms)/7.5 or 390 mV rms.
Filtering
An important aspect of rms-dc conversion is the need for averaging (the function is root-MEAN-square). For complex RF waveforms such as occur in CDMA, the filtering provided by the on-chip low-pass filter, while satisfactory for CW signals above 100 MHz, will be inadequate when the signal has modulation components that extend down into the kilohertz region. For this reason, the FLTR pin is provided: a capacitor attached between this pin and VPOS can extend the averaging time to very low frequencies.
Offset
An offset voltage can be added to the output (when using the micro_SOIC version) to allow the use of A/D converters whose range does not extend down to ground. However, accuracy at the low end will be degraded because of the inherent error in this added voltage. This requires that the pin IREF (internal reference) should be tied to VPOS and SREF (supply reference) to ground. In the IREF mode, the intercept is generated by an internal reference cell, and is a fixed 350 mV, independent of the supply voltage. To enable this intercept, IREF should be open-circuited, and SREF should be grounded. In the SREF mode, the voltage is provided by the supply. To implement this mode, tie IREF to VPOS and SREF to VPOS. The offset is then proportional to the supply voltage, and is 400 mV for a 3 V supply and 667 mV for a 5 V supply.
USING THE AD8361 Basic Connections
Figures 32, 33, and 34 show the basic connections for the micro_SOIC version AD8361 in its three operating modes. In all modes, the device is powered by a single supply of between 2.7 V and 5.5 V. The VPOS pin is decoupled using 100 pF and 0.01 F capacitors. The quiescent current of 1.1 mA in operating mode can be reduced to 1 A by pulling the PWDN pin up to VPOS. A 75 external shunt resistance combines with the ac-coupled input to give an overall broadband input impedance near 50 . Note that the coupling capacitor must be placed between the input and the shunt impedance. Input impedance and input coupling are discussed in more detail below. The input coupling capacitor combines with the internal input resistance (Figure 13) to give a high-pass corner frequency given by the equation
f3 dB =
1 2 x CC x RIN
REV. A
-9-
AD8361
With the 100 pF capacitor shown in Figures 32-34, the highpass corner frequency is about 8 MHz.
+VS 2.7 - 5.5V
the output headroom decreases. The response for lower supply voltages is similar (in the supply referenced mode, the offset is smaller), but the dynamic range will be reduced further, as headroom decreases. Figure 36 shows the response of the AD8361 to a CW input for various supply voltages.
5.0 SUPPLY REF 4.5
100pF 0.01 F 1 CC 100pF 2 3 R1 75 4
AD8361
VPOS IREF RFIN PWDN SREF 8 V rms VRMS 7
3.5 4.0
INTERNAL REF
RFIN
OUTPUT - Volts
FLTR 6 CFLTR COMM 5
3.0 2.5 2.0 1.5
GROUND REF
Figure 32. Basic Connections for Ground Referenced Mode
+VS 2.7 - 5.5V
1.0 0.5
100pF 0.01 F 1 2 RFIN R1 75 CC 3 100pF 4 PWDN COMM 5 RFIN FLTR 6 CFLTR
0.0
0
AD8361
VPOS IREF SREF 8 V rms VRMS 7
0.1
0.2
0.3 0.4 0.5 INPUT - V rms
0.6
0.7
0.8
Figure 35. Output Swing for Ground, Internal and Supply Referenced Mode. VPOS = 5 V (micro_SOIC Only)
5.5 5.0 4.5 5.0V 3.0V 3.5 3.0 2.5 2.0 1.5 2.7V 5.5V
Figure 33. Basic Connections for Internal Reference Mode
+VS 2.7 - 5.5V
OUTPUT - Volts
4.0
100pF 0.01 F 1 2 RFIN R1 75 CC 3 100pF 4 PWDN COMM 5 RFIN FLTR 6 CFLTR
AD8361
VPOS IREF SREF 8 V rms VRMS 7
1.0 0.5 0.0 0 0.1 0.2 0.3 0.4 0.5 INPUT - V rms 0.6 0.7 0.8
Figure 34. Basic Connections for Supply Referenced Mode
Figure 36. Output Swing for Supply Voltages of 2.7 V, 3.0 V, 5.0 V and 5.5 V (micro_SOIC Only)
Dynamic Range
The output voltage is nominally 7.5 times the input rms voltage (a conversion gain of 7.5 V/V rms). Three different modes of operation are set by the pins SREF and IREF. In addition to the ground referenced mode shown in Figure 32, where the output voltage swings from around near ground to 4.9 V on a 5.0 V supply, two additional modes allow an offset voltage to be added to the output. In the internal reference mode, (Figure 33), the output voltage swing is shifted upward by an internal reference voltage of 350 mV. In supply referenced mode (Figure 34), an offset voltage of VS/7.5 is added to the output voltage. Table I summarizes the connections, output transfer function and minimum output voltage (i.e., zero signal) for each mode.
Output Swing
Because the AD8361 is a linear responding device with a nominal transfer function of 7.5 V/V rms, the dynamic range in dB is not clear from plots such as Figure 35. As the input level is increased in constant dB steps, the output step size (per dB) will also increase. Figure 37 shows the relationship between the output step size (i.e., mV/dB) and input voltage for a nominal transfer function of 7.5 V/V rms.
Table I. Connections and Nominal Transfer Function for Ground, Internal, and Supply Reference Modes
Reference Mode Ground Internal Supply Output Intercept (No Signal) Zero 0.350 V VS/7.5
Figure 35 shows the output swing of the AD8361 for a 5 V supply voltage for each of the three modes. It is clear from Figure 35, that operating the device in either internal reference mode or supply referenced mode, will reduce the effective dynamic range as
IREF VPOS OPEN VPOS
SREF COMM COMM VPOS
Output 7.5 VIN 7.5 VIN + 0.350 V 7.5 VIN + VS/7.5
-10-
REV. A
AD8361
700 600 500 400
300 200 100 0
A number of options exist for input matching. For operation at multiple frequencies, a 75 shunt to ground, as shown in Figure 39a, will provide the best overall match. For use at a single frequency, a resistive or a reactive match can be used. By plotting the input impedance on a Smith Chart, the best value for a resistive match can be calculated. The VSWR can be held below 1.5 at frequencies up to 1 GHz, even as the input impedance varies from part to part. (Both input impedance and input capacitance can vary by up to 20% around their nominal values.) At very high frequencies (i.e., 1.8 GHz to 2.5 GHz), a shunt resistor will not be sufficient to reduce the VSWR below 1.5. Where VSWR is critical, remove shunt component and insert an inductor in series with the coupling capacitor as shown in Figure 39b.
0 100 200 300 400 500 INPUT - mV 600 700 800
mV/dB
Figure 37. Idealized Output Step Size as Function of Input Voltage
Table II gives recommended shunt resistor values for various frequencies and series inductor values for high frequencies. The coupling capacitor, CC, essentially acts as an ac-short and plays no intentional part in the matching.
CC RFIN RSH RFIN
Plots of output voltage vs. input voltage result in a straight line. It may sometimes be more useful to plot the error on a logarithmic scale, as shown in Figure 38. The deviation of the plot for the ideal straight line characteristic is caused by output clipping at the high end and by signal offsets at the low end. It should however be noted that offsets at the low end can be either positive or negative, so that this plot could also trend upwards at the low end. Figures 5, 6, 8, and 9 show a 3 sigma distribution of device error for a large population of devices.
2.0 1.5 1.0 2.5GHz
ERROR - dB
AD8361
a. Broadband Resistor Match
LM RFIN
CC RFIN
AD8361
b. Series Inductor Match
0.5 100MHz 0.0 1.9GHz -0.5 100MHz -1.0 RFIN
CM
CC RFIN LM
AD8361
c. Narrowband Reactive Match
-1.5 900MHz -2.0 0.01 0.02 (-21dBm) 0.1 (-7dBm) INPUT - V rms 0.4 (+5dBm) 1.0
RFIN
RSERIES
CC RFIN
Figure 38. Representative Unit, Error in dB vs. Input Level, VS = 2.7 V
AD8361
It is also apparent in Figure 38 that the error plot tends to shift to the right with increasing frequency. Because the input impedance decreases with frequency, the voltage actually applied to the input will also tend to decrease (assuming a constant source impedance over frequency). The dynamic range is almost constant over frequency, but with a small decrease in conversion gain at high frequency.
Input Coupling and Matching
d. Attenuating the Input Signal Figure 39. Input Coupling/Matching Options
Table II. Recommended Component Values for Resistive or Inductive Input Matching (Figures 39a and 39b)
Frequency 100 MHz 800 MHz 900 MHz 1800 MHz 1900 MHz 2500 MHz
Matching Component 63.4 Shunt 75 Shunt 75 Shunt 150 Shunt or 4.7 nH Series 150 Shunt or 4.7 nH Series 150 Shunt or 2.7 nH Series
The input impedance of the AD8361 decreases with increasing frequency in both its resistive and capacitive components (Figure 13). The resistive component varies from 225 at 100 MHz down to about 95 at 2.5 GHz.
REV. A
-11-
AD8361
Alternatively, a reactive match can be implemented using a shunt inductor to ground and a series capacitor as shown in Figure 39c. A method for hand calculating the appropriate matching components is shown on page 12 of the AD8306 data sheet. Matching in this manner results in very small values for CM, especially at high frequencies. As a result, a stray capacitance as small as 1 pF can significantly degrade the quality of the match. The main advantage of a reactive match is the increase in sensitivity that results from the input voltage being "gained up" (by the square root of the impedance ratio) by the matching network. Table III shows recommended values for reactive matching.
Table III. Recommended Values for a Reactive Input Match (Figure 39c)
provides adequate filtering for all frequencies above 240 MHz (i.e., ten times the frequency at the output of the squarer, which is twice the input frequency). However, signals with high peakto-average ratios, such as CDMA or W-CDMA signals, and with low frequency components, require additional filtering. TDMA signals, such as GSM, PDC, or PHS have a peak-toaverage ratio that is close to that of a sinusoid, and the internal filter is adequate. The filter capacitance of the AD8361 can be augmented by connecting a capacitor between Pin 6 (FLTR) and VPOS. Table IV shows the effect of several capacitor values for various communications standards with high peak-to-average ratios along with the residual ripple at the output, in peak-to-peak and rms volts. Note that large filter capacitors will increase the enable and pulse response times, as discussed below.
Table IV. Effect of Waveform and CFILT on Residual AC
Frequency MHz 100 800 900 1800 1900 2500
CM pF 16 2 2 1.5 1.5 1.5
LM nH 180 15 12 4.7 4.7 3.3
Waveform IS95 Reverse Link
CFILT Open 0.01 F
Output V dc 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0
Residual AC mV p-p mV rms 550 1000 2000 40 160 430 20 40 110 290 975 2600 50 190 670 225 940 2500 45 165 550 100 180 360 6 20 60 3 6 18 40 150 430 7 30 95 35 135 390 6 25 80
Input Coupling Using a Series Resistor
Figure 39d shows a technique for coupling the input signal into the AD8361, which may be applicable where the input signal is much larger than the input range of the AD8361. A series resistor combines with the input impedance of the AD8361 to attenuate the input signal. Since this series resistor forms a divider with the frequency-dependent input impedance, the apparent gain changes greatly with frequency. However, this method has the advantage of very little power being "tapped off" in RF power transmission applications. If the resistor is large compared to the transmission line's impedance then the VSWR of the system is relatively unaffected.
250 1.7
0.1 F IS95 8-Channel Forward Link 0.01 F 0.1 F W-CDMA 15 Channel 0.01 F 0.1 F
200
1.4
CAPACITANCE - pF
RESISTANCE -
150
1.1
Operation at Low Frequencies
100
0.8
50
0.5
0
0
500
1000
1500 2000 2500 FREQUENCY - MHz
3000
0.2 3500
Although the AD8361 is specified for operation up to 2.5 GHz, there is no lower limit on the operating frequency. It is only necessary to increase the input coupling capacitor to reduce the corner frequency of the input high-pass filter (use an input resistance of 225 for frequencies below 100 MHz). It is also necessary to increase the filter capacitor so that the signal at the output of the squaring circuit is free of ripple. The corner frequency will be set by the combination of the internal resistance of 2 k and the external filter capacitance.
Power Consumption, Enable and Power-On
Figure 40. Input Impedance vs. Frequency, Supply 3 V, SOT-23-6L
Selecting the Filter Capacitor
The AD8361's internal 27 pF filter capacitor is connected in parallel with an internal resistance that varies with signal level from 2 k for small signals to 500 for large signals. The resulting low-pass corner frequency between 3 MHz and 12 MHz
The quiescent current consumption of the AD8361 varies with the size of the input signal from about 1 mA for no signal up to 7 mA at an input level of 0.66 V rms (9.4 dBm re 50 ). If the input is driven beyond this point, the supply current increases steeply (see Figure 12). There is little variation in quiescent current with power supply voltage.
-12-
REV. A
AD8361
The AD8361 can be disabled either by pulling the PWDN (Pin 4) to VPOS or by simply turning off the power to the device. While turning off the device obviously eliminates the current consumption, disabling the device reduces the leakage current to less than 1 A. Figures 23 and 24 show the response of the output of the AD8361 to a pulse on the PWDN pin, with no capacitance and with a filter capacitance of 0.01 F respectively; the turn-on time is a function of the filter capacitor. Figure 27 shows a plot of the output response to the supply being turned on (i.e., PWDN is grounded and VPOS is pulsed) with a filter capacitor of 0.01 F Again, the turn-on time is strongly influenced by the size of the filter capacitor. If the input of the AD8361 is driven while the device is disabled (PWDN = VPOS), the leakage current of less than 1 A will increase as a function of input level. When the device is disabled, the output impedance increases to around 16 k.
Volts to dBm Conversion
current is required (>10 mA), the AD8051, which also has railto-rail capability, can be used, down to a supply voltage of 3 V. It can deliver up to 45 mA of output current.
5V 0.01 F 100pF
0.01 F VPOS VOUT AD8031 15V/V rms
AD8361
COMM PWDN
5k 5k
a. Slope of 15 V/V rms
5V 0.01 F 100pF 10k VPOS VOUT 5k 0.01 F
In many of the plots, the horizontal axis is scaled in both rms volts and dBm. In all cases, dBm are calculated relative to an impedance of 50 . To convert between dBm and volts in a 50 . system, the following equations can be used. Figure 40 shows this conversion in graphical form.
(V rms )2 50 Power ( dBm ) = 10 log 0.001 W 2 = 10 log (20 (V rms ) )
AD8361
5k COMM PWDN AD8031 3.75V/V rms
b. Slope of 3.75 V/V rms
5V 0.01 F 100pF 0.01 F VOUT
V rms =
dBm 0.001 W x 50 x log -1 = 10
log -1 dBm / 10 20
(
)
VPOS
AD8361
COMM PWDN
AD8031
7.5V/V rms
V rms 1
dBm +20 +10 0
c. Slope of 7.5 V/V rms Figure 42. Output Buffering Options
OUTPUT REFERENCE TEMPERATURE DRIFT COMPENSATION
0.1
-10 -20
0.01
-30 -40
0.001
Figure 41. Conversion from dBm to rms Volts
Output Drive Capability and Buffering
The error due to low temperature drift of the AD8361 can be reduced if the temperature is known. Many systems incorporate a temperature sensor; the output of the sensor is typically digitized, facilitating a software correction. Using this information, only a two-point calibration at ambient is required. The output voltage of the AD8361 at ambient (25C) can be expressed by the equation:
The AD8361 is capable of sourcing an output current of approximately 3 mA. If additional current is required, a simple buffering circuit can be used as shown in Figure 42c. Similar circuits can be used to increase or decrease the nominal conversion gain of 7.5 V/V rms (Figure 42a and 42b). In Figure 42b, the AD8031 buffers a resistive divider to give a slope of 3.75 V/V rms. In Figure 42a, the op amp's gain of two increases the slope to 15 V/V rms. Using other resistor values, the slope can be changed to an arbitrary value. The AD8031 rail-to-rail op amp, used in these examples can swing from 50 mV to 4.95 V on a single 5 V supply and operate at supply voltages down to 2.7 V. If high output REV. A
VOUT = GAIN x VIN + VOS
where GAIN is the conversion gain in V/V rms and VOS is the extrapolated output voltage for an input level of 0 V. GAIN and VOS (also referred to as Intercept and Output Reference) can be calculated at ambient using a simple two-point calibration; that is, by measuring the output voltages for two specific input levels. Calibration at roughly 35 mV rms (-16 dBm) and 250 mV rms (+1 dBm) is recommended for maximum linear dynamic range. However, alternative levels and ranges can be -13-
(
)
AD8361
chosen to suit the application. GAIN and VOS are then calculated using the equations:
VOUT = GAIN x VIN + VOS + DRIFTVOS x TEMP - 25C
(
)
(
)
(V GAIN = (V
OUT 2 IN 2
- VOUT1 - VIN 1
)
)
The equation can be rewritten to yield a temperature compensated value for VIN.
VIN =
VOS = VOUT1 - GAIN x VIN 1
(
)
(V
OUT
- VOS - DRIFTVOS x TEMP - 25C GAIN
(
))
Both GAIN and VOS drift over temperature. However, the drift of VOS has a bigger influence on the error relative to the output. This can be seen by inserting data from Figures 14 and 17 (conversion gain and intercept drift) into the equation for VOUT. These plots are consistent with Figures 10 and 11 which show that the error due to temperature drift decreases with increasing input level. This results from the offset error having a diminishing influence with increasing level on the overall measurement error. From Figure 14, the average Intercept drift is 0.43 mV/C from -40C to +25C and 0.17 mV/C from +25C to +85C. For a less rigorous compensation scheme, the average drift over the complete temperature range can be calculated: 0.010 V - ( -0.028 V ) DRIFTVOS ( V / C ) = +85C - ( -40C ) = 0.000304 V/C With the drift of VOS included, the equation for VOUT becomes:
EVALUATION BOARD
Figures 43 and 46 show the schematic of the AD8361 evaluation board. Note that uninstalled components are drawn in as dashed. The layout and silkscreen of the component side are shown in Figures 44, 45, 47, and 48. The board is powered by a single supply in the range, 2.7 V to 5.5 V. The power supply is decoupled by 100 pF and 0.01 F capacitors. Additional decoupling, in the form of a series resistor or inductor in R6, can also be added. Table V details the various configuration options of the evaluation board.
Table V. Evaluation Board Configuration Options
Component TP1, TP2 SW1
Function Ground and Supply Vector Pins. Device Enable. When in Position A, the PWDN pin is connected to +VS and the AD8361 is in power-down mode. In Position B, the PWDN pin is grounded, putting the device in operating mode. Operating Mode. Selects either Ground Referenced Mode, Internal Reference Mode or Supply Reference Mode. See Table I for more details. Input Coupling. The 75 resistor in position R2 combines with the AD8361's internal input impedance to give a broadband input impedance of around 50 . For more precise matching at a particular frequency, R2 can be replaced by a different value (see Input Matching and Figure 39). Capacitor C1 ac-couples the input signal and creates a high-pass input filter whose corner frequency is equal to approximately 8 MHz. C1 can be increased for operation at lower frequencies. If resistive attenuation is desired at the input, series resistor R1, which is nominally 0 , can be replaced by an appropriate value. Power Supply Decoupling. The nominal supply decoupling of 0.01 F and 100 pF. A series inductor or small resistor can be placed in R6 for additional decoupling. Filter Capacitor. The internal 50 pF averaging capacitor can be augmented by placing a capacitance in C5. Output Loading. Resistors and capacitors can be placed in C4 and R5 to load test V rms.
Default Condition Not Applicable SW1 = B
SW2/SW3 C1, R2
SW2 = A, SW3 = B (Ground Reference Mode) R2 = 75 (Size 0402) C1 = 100 pF (Size 0402)
C2, C3, R6
C5 C4, R5
C2 = 0.01 F (Size 0402) C3 = 100 pF (Size 0402) R6 = 0 (Size 0402) C5 = 1 nF (Size 0603) C4 = R5 = Open (Size 0603)
-14-
REV. A
AD8361
VPOS TP2 R6 0 VS A B RFIN R2 75 VPOS A B SW1 SW2 C1 100pF C2 0.01 F C3 100pF VS SW3 A B R4 0 R5 VPOS 1nF 4 PWDN COMM 5 TP1
(OPEN)
C3 100pF J2 R4 0 1 C4
OPEN
C2 0.01 F
AD8361
VRMS VPOS RFIN PWDN 6 5 4 C1 100pF R2 75 3 2 R7 50 TP2 VPOS J1 2 COMM 3 C5 1nF TP1 J3 1 SW1 FLTR R5
OPEN
AD8361
1 VPOS 2 IREF 3 RFIN SREF 8 VRMS 7 C5 FLTR 6
C4
(OPEN)
Vrms
Figure 43. Evaluation Board Schematic micro_SOIC
Figure 46. Evaluation Board Schematic, SOT-23-6L
Figure 44. Layout of Component Side micro_SOIC
Figure 47. Layout of the Component Side, SOT-23-6L
Figure 45. Silkscreen of Component Side micro_SOIC
Figure 48. Silkscreen of the Component Side, SOT-23-6L
REV. A
-15-
AD8361
Problems caused by impedance mismatch may arise using the evaluation board to examine the AD8361 performance. One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source, cable, and cable interconnection, as well as those occurring on the evaluation board can cause these problems. A simple (and common) example of such problem is triple travel due to mismatch at both the source and the evaluation board. Here the signal from the source reaches the evaluation board and mismatch causes a reflection. When that reflection reaches the source mismatch, it causes a new reflection, which travels back to the evaluation board adding to the original signal incident at the board. The resultant voltage will vary with both cable length and frequency dependent upon the relative phase of the initial and reflected signals. Placing the 3 dB pad at the input of the board improves the match at the board and thus reduces the sensitivity to mismatches at the source. When such precautions are taken, measurements will be less sensitive to cable length and other fixturing issues. In an actual application when the distance between AD8361 and source is short and well defined, this 3 dB attenuator is not needed.
CHARACTERIZATION SETUPS Equipment
Error from 25C performance uses the performance of a given device and waveform type as the reference; it is predominantly a measure of output variation with temperature.
C4 0.1 F C2 100pF
AD8361
VPOS IREF RFIN R1 75 PWDN C1 0.1 F 1 2 3 4 VPOS IREF RFIN PWDN SREF 8 VRMS 7 C3 FLTR 6 COMM 5 SREF VRMS
The primary characterization setup is shown in Figure 50. The signal source used was a Rohde & Schwarz SMIQ03B, version 3.90HX. The modulated waveforms used for IS95 reverse link, IS95 nine active channels forward (Forward Link 18 setting), W-CDMA 4- and 15-channel were generated using the default settings coding and filtering. Signal levels were calibrated into a 50 impedance.
Analysis
Figure 49. Characterization Board
AD8361
CHARACTERIZATION BOARD SMIQ038B RF SOURCE RF SIGNAL RFIN 3dB ATTENUATOR PRUP DC SOURCES IEEE BUS PC CONTROLLER DC MATRIX / DC SUPPLIES / DMM +VS SREF IREF VRMS DC OUTPUT
The conversion gain and output reference are derived using the coefficients of a linear regression performed on data collected in its central operating range (35 mV rms to 250 mV rms). This range was chosen to avoid areas of operation where offset distorts the linear response. Error is stated in two forms Error from Linear Response to CW waveform and Output Delta from 25C performance.
Figure 50. Characterization Setup
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.122 (3.10) 0.114 (2.90)
0.122 (3.10) 0.106 (2.70)
8
5
0.122 (3.10) 0.114 (2.90)
1 4
0.193 (4.90) BSC
0.071 (1.80) 0.059 (1.50) PIN 1
6 1
5 2
4 3
0.118 (3.00) 0.098 (2.50)
PIN 1 0.0256 (0.65) BSC 0.006 (0.15) 0.002 (0.05) 0.016 (0.40) 0.010 (0.25) 0.043 (1.10) MAX 6 0 SEATING 0.009 (0.23) PLANE 0.005 (0.13)
0.037 (0.95) 0.030 (0.75)
0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.035 (0.90) 0.006 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE 10 0.009 (0.23) 0 0.003 (0.08) 0.022 (0.55) 0.014 (0.35)
0.028 (0.70) 0.016 (0.40)
-16-
REV. A
PRINTED IN U.S.A.
8-Lead micro_SOIC Package (RM-8)
6-Lead SOT-23-6L Package (RT-6)
C3716a-2-6/00 (rev. A) 01088
The Error from Linear Response to CW waveform is the difference in output from the ideal output defined by the conversion gain and output reference. This is a measure of both the linearity of the device response to both CW and modulated waveforms. The error in dB uses the conversion gain multiplied times the input as its reference. Error from Linear Response to CW waveform is not a measure of absolute accuracy, since it is calculated using the gain and output reference of each device. But it does show the linearity and effect of modulation on the device response.

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